Toshiba Corp. on Feb. 23 announced breakthroughs in NAND flash technology that secure major advances in chip density and performance.
In the 19-nanometer generation, Toshiba has developed a 3-bit-per-cell 128-gigabit chip with the world's smallest die size (170 square millimeters) and fastest write speed (18 MB/s) of any 3-bit-per-cell device. The chip entered mass production earlier this month and Toshiba and its technology partner, SanDisk, unveiled its key technology advances at the International Solid State Circuits Conference in San Francisco on Feb. 22.
Manufacturers of NAND flash memories must respond to demand for higher densities at competitive costs for such applications as USB memories and memory cards.
The new 3-bit-per-cell 19-nm generation device uses the three-step programming algorithm and air-gap technology for transistors, effectively reducing coupling between memory cells down to 5 percent, achieving a write speed performance of 18 MB/s. In three-step writing technology, it writes through rough distribution in the second step, and tightens as well-defined distribution at the third.
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